ترکیب

ترکیب

اسلاید 1: مرتضي صاحب الزماني 1Synthesis

اسلاید 2: مرتضي صاحب الزماني 2What is Synthesis?Transformation of an abstract description into a more detailed description + operator is transformed into a gate netlist if (VEC_A = VEC_B) then is realized as a comparator which controls a multiplexer Transformation depends on several factors عملگرهاي ساده (مثل AND، OR، مقايسه) به گيتهاي مشخصي تبديل مي شوند اما عملگرهاي پيچيده تر مثل ضرب ابتدا به ماکروسلهاي خاص آن tool تبديل مي شوند.

اسلاید 3: مرتضي صاحب الزماني 3Field Programmable Gate Array (FPGA)

اسلاید 4: مرتضي صاحب الزماني 4چرخه ي طراحي براي FPLDها مزايا: کوتاه شدن پروسه ي طراحي. نوآوري بيشتر (پروسه ي طراحي به مراحل بالاتر رفتاري منتقل مي شود) (تشابه با زبانهاي سطح بالا) Debug طرح بسيار آسانتر و سريعتر. مانند سيکل برنامه نويسي: تغييرات در طرح بسيار آسانتر.کامپايلاجرابرنامه نويسيويرايشکامپايلشبيه سازيورود طرحويرايشسنتزشبيه سازيويرايش

اسلاید 5: مرتضي صاحب الزماني 5SynthesizabilityOnly a subset of VHDL is synthesizable Different Tools support different subsets records? arrays of integers? clock edge detection? sensitivity list? ...

اسلاید 6: مرتضي صاحب الزماني 6Different Language Support for Synthesis

اسلاید 7: مرتضي صاحب الزماني 7How to Do?Macrocells adder comparator Bus interface Constraints speed area power Optimizations boolean: mathematic gate: technological

اسلاید 8: مرتضي صاحب الزماني 8Non-functional requirementsPerformance:Clock speed is generally a primary requirement.Usually expressed as a lower bound.Design cycle and Timing ClosureSize:Determines manufacturing cost.If your design doesn’t fit into one size FPGA, you must use the next larger FPGA.For very large designs: multi-FPGAs.Power/energy:Power/Energy related to battery life and heat.May have more cost:More expensive packaging to dissipate heat.More extreme measures (e.g. cooling fans).Many digital systems are power- or energy-limited.

اسلاید 9: مرتضي صاحب الزماني 9Mapping into an FPGAMust choose the FPGA:Capacity.Pinout/package type.Maximum speed.

اسلاید 10: مرتضي صاحب الزماني 10Synthesis Process in Practiceباوجود مکانيزمهاي بهينه سازي، ممکن است بعد از سنتز، همة محدوديتها برآورده نشده باشند  تکرار

اسلاید 11: مرتضي صاحب الزماني 11Path delayCombinational network delay is measured over paths through network.Can trace a causality chain from inputs to worst-case output.

اسلاید 12: مرتضي صاحب الزماني 12Path delay examplenetworkgraph model

اسلاید 13: مرتضي صاحب الزماني 13Critical pathCritical path = path which creates longest delay.Can trace transitions which cause delays that are elements of the critical delay path.

اسلاید 14: مرتضي صاحب الزماني 14Critical path through delay graph

اسلاید 15: مرتضي صاحب الزماني 15Delay Paths in a design

اسلاید 16: مرتضي صاحب الزماني 16False pathsLogic gates are not simple nodes—some input changes don’t cause output changes.A false path is a path which never happens due to Boolean gate conditions.False paths cause pessimistic delay estimates.

اسلاید 17: مرتضي صاحب الزماني 17Placement and delayPlacement helps determine routing.Routing determines wire length.Wire length determines capacitive load.Capacitive load determines delay.

اسلاید 18: مرتضي صاحب الزماني 18Example: Adder placement and delayN-bit adder: (optimal placement)++++

اسلاید 19: مرتضي صاحب الزماني 19Bad placement and routingplacementroutingWith no delay constraints.

اسلاید 20: مرتضي صاحب الزماني 20Bad placement and routingAdder has been distributed throughout the FPGA.I/O pins have been spread around the chip. P&R algorithms do not catch on to regularity.

اسلاید 21: مرتضي صاحب الزماني 21Better placement and routingWith delay constraints. Better but far from optimal (less spread out horizontally but spread out vertically)

اسلاید 22: مرتضي صاحب الزماني 22How to improve?Use macros (optimized),Put constraints on the placement of objects,Hand place objects.Example: later.

اسلاید 23: مرتضي صاحب الزماني 23Power Optimization

اسلاید 24: مرتضي صاحب الزماني 24Power optimizationTransitions cause power consumption.Logic network design helps control power consumption:minimizing capacitance;eliminating unnecessary glitches.

اسلاید 25: مرتضي صاحب الزماني 25Power optimizationLeakage in more advanced processes.Even when logic is idle.The only way: disconnect the power supply from the logic when not needed for some time.It generally takes a considerable period (larger than a clock period) to reconnect power and let the circuits stabilize.

اسلاید 26: مرتضي صاحب الزماني 26Glitching exampleGate network:

اسلاید 27: مرتضي صاحب الزماني 27Glitching example behaviorNOR gate produces 0 output at beginning and end:beginning: bottom input is 1;end: NAND output is 1;Difference in delay between application of primary inputs and generation of new NAND output causes glitch.

اسلاید 28: مرتضي صاحب الزماني 28Adder Chain Glitchingbadgooda+bcda+ba+b+cc+da+ba+b+ca+b+c+d

اسلاید 29: مرتضي صاحب الزماني 29ExplanationUnbalanced chain has signals arriving at different times at each adder.A glitch downstream propagates all the way upstream.Balanced tree introduces multiple glitches simultaneously, reducing total glitch activity.

اسلاید 30: مرتضي صاحب الزماني 30Factorization for low powerProper factorization reduces glitching.badgoodacaca: High transition probability

اسلاید 31: مرتضي صاحب الزماني 31Factorization techniquesIn example, a has high transition probability, b and c low probabilities.Reduce number of logic levels through which high-probability signals must travel in order to reduce propagation of glitches.

اسلاید 32: مرتضي صاحب الزماني 32Example (ALU)ALU output is not used for every cycle If ALU inputs change, the energy is needlessly consumed

اسلاید 33: مرتضي صاحب الزماني 33Example (ALU)Control Signal selects whether data is allowed to pass the logic or the previous value is held to avoid transitions.LogicDQDataControl

اسلاید 34: مرتضي صاحب الزماني 34Layout for low powerPlace and route to minimize capacitance of nodes with high glitching activity.Feed back wiring capacitance values to power analysis for better estimates.

اسلاید 35: مرتضي صاحب الزماني 35State assignment for low powerLater

اسلاید 36: مرتضي صاحب الزماني 36Case Study16 x 16 multiplier example.

اسلاید 37: مرتضي صاحب الزماني 37The FPGA design processXilinx ISE (Integrated Synthesis Environment)Translation from HDL.(Synthesis, Translation)Logic synthesis.(Mapping)Placement and routing.(Place and Route)Configuration generation.(Program File Generation)

اسلاید 38: مرتضي صاحب الزماني 38Design experimentsSynthesize with no constraints.Synthesize with timing constraint.Tighten timing constraint.Synthesize with placement constraints.Power:Many tools don’t allow us to directly specify power consumption  must rewrite our h/w description for better power consumption characteristics.

اسلاید 39: مرتضي صاحب الزماني 39Post-translation simulation modelNo timing or area constraintsHDL model in terms of FPGA primitives.Example: X_LUT4 p12_Madd__n0015_Mxor_Result_Xo<1>1 ( .ADR0(x_7_IBUF), .ADR1(y_13_IBUF), .ADR2(c12[7]), .ADR3(row12[8]), .O(row13[7]) );

اسلاید 40: مرتضي صاحب الزماني 40Mapping reportDesign Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 501 out of 1,024 48%Logic Distribution: Number of occupied Slices: 255 out of 512 49% Number of Slices containing only related logic: 255 out of 255 100% Number of Slices containing unrelated logic: 0 out of 255 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 501 out of 1,024 48% Number of bonded IOBs: 64 out of 92 69%Total equivalent gate count for design: 3,006Additional JTAG gate count for IOBs: 3,072Peak Memory Usage: 64 MB

اسلاید 41: مرتضي صاحب الزماني 41Related vs. Unrelated Logic (Hidden)Related logic: logic that shares connectivity. Unrelated logic: logic that shares no connectivity.When assembling slices, mapper gives priority to combine logic that is related best results.Mapper will only begin packing unrelated logic into a slice once all of the slices are occupied.

اسلاید 42: مرتضي صاحب الزماني 42Static timing analysis reportTiming constraint: TS_P2P = MAXDELAY FROM TIMEGRP PADS TO TIMEGRP PADS 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns.--------------------------------------------------------------------------------After Mapping:  estimated delays (no information about interconnects)

اسلاید 43: مرتضي صاحب الزماني 43Static timing report: delays along pathsData Sheet report:-----------------All values displayed in nanoseconds (ns)Pad to Pad------------------+----------------------+-----------+Source Pad |Destination Pad| Delay |------------------+----------------------+-----------+x<0> |p<0> | 5.824|x<0> |p<10> | 10.675|x<0> |p<11> | 11.214|x<0> |p<12> | 11.753|

اسلاید 44: مرتضي صاحب الزماني 44Routing reportPhase 1: 1975 unrouted; REAL time: 11 secs Phase 2: 1975 unrouted; REAL time: 11 secs Phase 3: 619 unrouted; REAL time: 12 secs Phase 4: 619 unrouted; (0) REAL time: 12 secs Phase 5: 619 unrouted; (0) REAL time: 12 secs Phase 6: 619 unrouted; (0) REAL time: 12 secs Phase 7: 0 unrouted; (0) REAL time: 12 secs The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0REAL time: Routing algorithm run time.

اسلاید 45: مرتضي صاحب الزماني 45Static timing after routingTiming constraint: TS_P2P = MAXDELAY FROM TIMEGRP PADS TO TIMEGRP PADS 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 38.424ns.-------------------------------------------------------------------(vs 20.916 ns in mapping report) Because of interconnect delays.

اسلاید 46: مرتضي صاحب الزماني 46Timing constraintUse timing constraint editor:

اسلاید 47: مرتضي صاحب الزماني 47Post-map static timing reportTiming constraint: TS_P2P = MAXDELAY FROM TIMEGRP PADS TO TIMEGRP PADS 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns.Pad to pad Hasn’t changed since this design has limited opportunities for logic synthesis to change delays by restructuring logic.

اسلاید 48: مرتضي صاحب الزماني 48Post-routing static timing reportTiming constraint: TS_P2P = MAXDELAY FROM TIMEGRP PADS TO TIMEGRP PADS 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 31.984ns.Tools generally try to meet the delay goal as closely as possible to minimize area.

اسلاید 49: مرتضي صاحب الزماني 49Tighter timing constraintsTighten requirement to 25 ns.Post-place-route timing report:Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP PADS TO TIMEGRP PADS 25 nS ; 20135312 items analyzed, 11 timing errors detected. (11 setup errors, 0 hold errors) Maximum delay is 31.128ns.

اسلاید 50: مرتضي صاحب الزماني 50Report on a violated pathSlack: -6.128ns (requirement - data path) Source: y<0> (PAD) Destination: p<30> (PAD) Requirement: 25.000ns Data Path Delay: 31.128ns (Levels of Logic = 31) Modify the logic and/or physical design to improve the delay.

اسلاید 51: مرتضي صاحب الزماني 51Power reportPower summary: I(mA) P(mW)----------------------------------------------------------------Total estimated power consumption: 333 --- Vccint 1.50V: 0 0 Vccaux 3.30V: 100 330 Vcco33 3.30V: 1 3 --- Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 0 0 Signals: 0 0 --- Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3Thermal summary:---------------------------------------------------------------- Estimated junction temperature: 36C Ambient temp: 25C Case temp: 35C Theta J-A: 34C/WHelps us determine whether we need additional cooling.

اسلاید 52: مرتضي صاحب الزماني 52Improving areaFloorplanner window:Floorplanner  View/edit placed designLEsChipfloorplanGreen rectangles: mapped components to CLBs

اسلاید 53: مرتضي صاحب الزماني 53Rat’s nest wiringIf you click on a component in the deign hierarchy window, its rat’s nest is shown.

اسلاید 54: مرتضي صاحب الزماني 54Routing editor viewFPGA Editor  View/Edit Routed Design

اسلاید 55: مرتضي صاحب الزماني 55Editing constraintsUse constraints editor to place constraints:This tool allws you to constrain the placement of logic as well as the assignment of chip I/Os to IOBs (e.g useful for PCB design)

اسلاید 56: مرتضي صاحب الزماني 56Design browser pane

اسلاید 57: مرتضي صاحب الزماني 57Drag and drop constraints

اسلاید 58: مرتضي صاحب الزماني 58Change the shape of constraints

اسلاید 59: مرتضي صاحب الزماني 59Full set of placement constraintsWe place the rows of the multiplier one below the other to create the row structure of the floorplan.

اسلاید 60: مرتضي صاحب الزماني 60Placement results

اسلاید 61: مرتضي صاحب الزماني 61New timing reportAfter placement constraints: 19742142 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 29.934ns.Compares to 31 ns for unconstrained placement.

اسلاید 62: مرتضي صاحب الزماني 62Combinational Process: Sensitivity ListLibrary IEEE; use IEEE.Std_Logic_1164.all;   entity IF_EXAMPLE is port (A, B, C, X : in std_ulogic_vector(3 downto 0);           Z                : out std_ulogic_vector(3 downto 0)); end IF_EXAMPLE;     architecture A of IF_EXAMPLE is begin      process (A, B, C, X)      begin         if ( X = 1110 ) then            Z <= A;         elsif (X = 0101) then            Z <= B;         else            Z <= C;         end if;      end process; end A;

اسلاید 63: مرتضي صاحب الزماني 63Combinational Process: Sensitivity Listprocess (A, B, SEL) begin   if SEL = `1` then     Z <= A;   else     Z <= B;   end if; end process;If SEL is missing in the sensitivity list, what will the behavior (simulation) be?Sensitivity list is usually ignored during synthesis.Equivalent behavior of simulation model and hardware All signals which are read are entered into the sensitivity list. Complete if-statement for the synthesis of combinational logic.

اسلاید 64: مرتضي صاحب الزماني 64Combinational Process: Incomplete AssignmentsLibrary IEEE; use IEEE.Std_Logic_1164.all;     entity INCOMP_IF is port (A, B, SEL :in std_ulogic;          Z              : out std_ulogic); end INCOMP_IF;     architecture RTL of INCOMP_IF is begin process (A, B, SEL) begin        if SEL = `1` then            Z <= A;        end if; end process; end RTL;Latchي كه هنگام SEL = ‘1’ شفاف است (Transparent latch).هم احتمالاٌ ناخواسته است هم در مدارهاي سنكرون FFها بهترند چون قبل از پايداري مدار تركيبي از مقادير سيگنالهاي مياني غير مجاز جلوگيري مي كند.What is the value of Z, if SEL = `0` ? What hardware would be generated during synthesis ?

اسلاید 65: مرتضي صاحب الزماني 65Modeling of Flip-FlopsLibrary IEEE; use IEEE.Std_Logic_1164.all;    entity FLOP is port (D, CLK        : in std_ulogic;          Q                  : out std_ulogic); end FLOP;    architecture A of FLOP is begin       process       begin           wait until CLK`event and CLK=`1`;           Q <= D;       end process; end A;

اسلاید 66: مرتضي صاحب الزماني 66Description of Rising Clock Edge for SynthesisStandard for synthesis: IEEE 1076.6... if condition RISING_EDGE ( clock_signal_ name) (not always supported) clock_signal_ nameEVENT and clock_signal _name=1 clock_signal _name=1 and clock_signal_ nameEVENT not clock_signal_ nameSTABLE and clock_signal_ name=1 clock_signal _name=1 and not clock_signal_ nameSTABLEسنتزكننده ها معمولاً ليست حساسيت را ناديده مي گيرند.همه ي waitها را هم پشتيباني نمي كنند. براي عناصرحافظه: if يا wait until به صورت خاص

اسلاید 67: مرتضي صاحب الزماني 67Description of Rising Clock Edge for Synthesis... wait until condition RISING_EDGE ( clock_signal_ name) clock_signal_ nameEVENT and clock_signal _name=1 clock_signal _name=1 and clock_signal_ nameEVENT not clock_signal_ nameSTABLE and clock_signal_ name=1 clock_signal _name=1 and not clock_signal_ nameSTABLE clock_signal _name=1IEEE 1076.6 is not yet fully supported by all tools

اسلاید 68: مرتضي صاحب الزماني 68Description of Rising Clock Edge for SynthesisIn Std_Logic_1164 packageprocess begin    wait until RISING_EDGE(CLK);    Q <= D; end process;function RISING_EDGE (signal CLK : std_ulogic)              return boolean is begin      if (  CLK`event and CLK =`1`                              and CLK`last_value=`0`) then          return true;      else          return false;      end if; end RISING_EDGE;

اسلاید 69: مرتضي صاحب الزماني 69Gated ClockDesigners avoid using gated clocks because of problematic timing behavior of the circuit (adds skew).Low power designs deliberately disable clocks to reduce or eliminate power waste by useless switching of transistors.process begin    wait until RISING_EDGE(CLK); if (DGATE) then    Q <= D; end process;muxDFFDGATECLKDQ

اسلاید 70: مرتضي صاحب الزماني 70Register InferenceLibrary IEEE; use IEEE.Std_Logic_1164.all;    entity COUNTER is port ( CLK    : in std_ulogic;            Q    : out integer  range 0 to 15 ); end COUNTER;    architecture A of COUNTER is   signal COUNT  : integer  range 0 to 15 ; begin    process (CLK)    begin       if CLK`event and CLK = `1` then          if (COUNT >= 9) then             COUNT <= 0;          else             COUNT <= COUNT +1;          end if;       end if;    end process;     Q <= COUNT; end A; شمارندة يك رقمي BCDFor all signals which receive an assignment in clocked processes, memory is synthesized.COUNT: 4 FF(constrained integer)Q not used in clocked process.اشكال: مكانيزم reset هنگام روشن شدن ندارد

اسلاید 71: مرتضي صاحب الزماني 71Asynchronous Set/ResetLibrary IEEE; use IEEE.Std_Logic_1164.all;    entity ASYNC_FF is port (    D, CLK, SET, RST : in std_ulogic;             Q                            : out std_ulogic); end ASYNC_FF;    architecture A of ASYNC_FF is begin     process  (CLK, RST, SET)     begin        if (RST = `1`) then           Q <= `0`;        elsif SET =1 then           Q <= 1;        elsif (CLK`event and CLK = `1`) then           Q <= D;        end if;     end process; end A;if/elsif - structure The last elsif has an edge No else براي set/reset سنكرون فقط clk در ليست حساسيت قرار مي گيرد (مي توان با wait until هم مدلسازي كرد).اما براي آسنكرون فقط با ليست حساسيت مي توان مدلسازي كردحتماً همة وروديهاي آسنكرون در ليست حساسيت وارد شوند والا نتيجة شبيه سازي با سنتز متفاوت مي شود.

اسلاید 72: مرتضي صاحب الزماني 72Coding Style Influence EXAMPLE1: process (SEL,A,B) begin    if SEL = `1` then       Z <= A + B;    else       Z <= A + C;    end if; end process EXAMPLE1;Direct implementationEXAMPLE2: process (SEL,A,B)     variable  TMP : bit; begin    if SEL = `1` then        TMP  := B;    else        TMP  := C;    end if;    Z <= A + TMP; end process EXAMPLE2;Manual resource sharingفقط يك جمع كننده نياز دارد.اگر SEL ديرتر مي رسد مدار بالايي سريعتر عمل مي كند.

اسلاید 73: مرتضي صاحب الزماني 73Source Code Optimization An operation can be described very efficiently for synthesis, e.g.:In one description the longest path goes via five, in the other description via three addition components - some optimization tools automatically change the description according to the given constraints.

اسلاید 74: مرتضي صاحب الزماني 74Source Code Optimization If one of the inputs arrives later than others, it can be chosen for IN6 in the left implementation.If power is a consideration, IN6 could be used for the signal that changes more frequently in the left implementation since it passes through only one adder.

اسلاید 75: مرتضي صاحب الزماني 75سنتز عملگرهابسته به عملگر و عناصر كتابخانه اي (برحسب گيتهاي استاندارد يا برحسب logic cellها (يا ماكروسلها در ASIC)) ماجولي در netlist ايجاد مي شود.اين ماجولها برحسب سرعت يا مساحت بهينه شده اند (كه كاربر مشخص مي كند)در بعضي سنتز كننده ها مي توان در كد VHDL commentهايي نوشت تا مثلاً Carry-Lookahead يا Ripple Carry انتخاب كند.

اسلاید 76: مرتضي صاحب الزماني 76Example: Adder entity ADD is    port (A, B  : in integer range 0 to 7;            Z       : out integer range 0 to 15); end ADD; architecture ARITHMETIC of ADD is begin     Z <= A + B; end ARITHMETIC;Notice: Advantages of a range declaration with integer types:    a) During simulation: check for out of range...    b) During synthesis: only 4 bit bus width library VENDOR_XY; use VENDOR_XY.p_arithmetic.all; entity MVL_ADD is    port (A, B : in stdlogic_vector (3 downto 0);             Z : out stdlogic_vector (4 downto 0) ); end MVL_ADD; architecture ARITHMETIC of MVL_ADD is begin     Z <= A + B; // not allowed end ARITHMETIC;

اسلاید 77: مرتضي صاحب الزماني 77IF Structure <-> CASE Structure · · · if (IN > 17) then     OUT <= A ; elsif (IN < 17) then    OUT <= B ; else    OUT <=  C ; end if ; · · ·Different descriptions may be synthesized differently · · · case IN is    when 0 to 16 =>           OUT <= B ;    when 17 =>           OUT <= C ;    when others =>           OUT <= A ; end case ; · · ·سنتزكننده ها ممكن است optimize كنند.

اسلاید 78: مرتضي صاحب الزماني 78Variables in Clocked Processes VAR_1: process(CLK)    variable TEMP : integer; begin        if (CLKevent and CLK = 1) then       TEMP := INPUT * 2;       OUTPUT_A <= TEMP + 1;       OUTPUT_B <= TEMP + 2;    end if; end process VAR_1;Registers are generated for all variables that might be read before they are updatedVAR_2: process(CLK)    variable TEMP : integer; begin        if (CLKevent and CLK = 1) then       OUTPUT <= TEMP + 1;       TEMP := INPUT * 2;    end if; end process VAR_2;How many registers are generated?

اسلاید 79: مرتضي صاحب الزماني 79ELSE for Clock Checking  process(CLK) begin   if (CLK`event and CLK=`1`) then     Q <= D; else Q <= A;  end if; end process;در بيشتر سنتز كننده ها اگر براي آشكارسازي كلاك, else به كار برده باشيم انجام نمي دهند (نمي دانند چطور بايد آن را سنتز كرد).

اسلاید 80: مرتضي صاحب الزماني 80Don’t Care  درشبيه سازها مقايسه با ‘-’ در شرطها عموماً نتيجة FALSE مي دهد (هيچگاه مقدار سيگنال = ‘-’ نمي شود):when (a = “1---”) ….اگر مثلاً a = “1000” شود شرط TRUE نمي شود.براي اين منظور مي توان از stdmatch(s1, s2) (در پکيج numeric_std) استفاده كرد:when (std_match(a, “1---”)) ….همة حالات ‘-’ را آزمايش مي كند.

اسلاید 81: مرتضي صاحب الزماني 81Synthesis Tips- Loops must have a fixed range - while constructs usually cannot be synthesized Shared variables: not to be used in synthesizable codeReal و character و time: غير قابل سنتزمحدود به testbench نويسي و مدلسازي.Some aggregate constructs may not be supported by your synthesis toolSynthesis tools map enumerations onto a suitable bit pattern automatically.

اسلاید 82: مرتضي صاحب الزماني 82Synthesis TipsArrays: Only integer index sets are supported by all synthesis toolsSome synthesizers support up to two dimensionsAliases are not always supported by synthesis toolsProcedures: Default parameters should not be used in synthesizable code (since some synthesizers initialize absent parameters with type’left  inconsistent with simulation)

اسلاید 83: مرتضي صاحب الزماني 83Finite State Machines and VHDL One- , two- or three-processesState Coding FSM Types Medvedev Moore Mealy Registered Output

اسلاید 84: مرتضي صاحب الزماني 84One-Process FSM FSM_FF: process (CLK, RESET) begin     if RESET=1 then          STATE <= START  ;     elsif CLKevent and CLK=1 then         case  STATE  is                 when  START   => if  X=GO_MID  then                                  STATE <= MIDDLE  ;                              end if ;                 when  MIDDLE  => if  X=GO_STOP  then                                  STATE <= STOP  ;                              end if ;                 when  STOP    => if  X=GO_START  then                                  STATE <= START  ;                              end if ;                 when  others  =>  STATE <= START  ;             end case ;     end if ; end process FSM_FF ;

اسلاید 85: مرتضي صاحب الزماني 85Two-Process FSM FSM_LOGIC: process ( STATE , X) begin      case  STATE  is            when  START   => if  X=GO_MID  then                             NEXT_STATE <= MIDDLE  ;                        end if ;            when  MIDDLE  => ...            when  others  =>  NEXT_STATE <= START  ;         end case ; end process FSM_LOGIC ;FSM_FF: process (CLK, RESET)    begin     if RESET=1 then          STATE <= START  ;     elsif CLKevent and CLK=1 then          STATE  <=  NEXT_STATE  ;     end if; end process FSM_FF ;

اسلاید 86: مرتضي صاحب الزماني 86How Many Processes? Structure and Readability Asynchronous combinatoric ≠ synchronous storing elements => 2 processes Graphical FSM (without output equations) resembles one state process => 1 process Simulation Error detection easier with two state processes due to access to intermediate signals. => 2 processes Synthesis 2 state processes can lead to smaller generic net list and therefore to better synthesis results (depends on synthesizer but in general, it is closer to hardware) => 2 processes

اسلاید 87: مرتضي صاحب الزماني 87State Encoding type STATE_TYPE is ( START, MIDDLE, STOP ) ; signal STATE : STATE_TYPE ;State encoding responsible for safety of FSM START      ->  00 MIDDLE   ->  01 STOP       ->  10 Default encoding: binary START     ->  001 MIDDLE   ->  010 STOP       ->  100 Speed optimized default encoding: one hot if {log2(# of states) ≠ log2(# of states) } => unsafe FSM!

اسلاید 88: مرتضي صاحب الزماني 88Encoding of CASE Statement type STATE_TYPE is (START, MIDDLE, STOP) ; signal STATE : STATE_TYPE ; · · ·     case STATE is            when START     => · · ·            when MIDDLE  => · · ·            when STOP      => · · ·             when others      => · · ·     end case ;Adding the when others choice Not necessarily safe; some synthesis tools will ignore when others choice

اسلاید 89: مرتضي صاحب الزماني 89Extension of Type Declarationtype STATE_TYPE is (START, MIDDLE, STOP, DUMMY) ; signal STATE : STATE_TYPE ; ···     case STATE is            when START     => ···            when MIDDLE  => ···            when STOP      => ···             when DUMMY      => ···     -- or when others     end case ;Adding dummy valuesOnly for binary encodingAdvantages: Safe FSM after synthesis{2 log2(# of states) - n} dummy states (n=20 => 12 dummy states)Changing to one hot coding => unnecessary hardware (n=20 => 12 unnecessary Flip Flops)

اسلاید 90: مرتضي صاحب الزماني 90Hand Codingsubtype STATE_TYPE is std_ulogic_vector (1 downto 0) ; signal STATE : STATE_TYPE ; constant START   : STATE_TYPE := 01; constant MIDDLE : STATE_TYPE := 11; constant STOP     : STATE_TYPE := 00; ···     case STATE is            when START     => ···            when MIDDLE  => ···            when STOP      => ···            when others      => ···     end case ;Defining constants Control of encoding Safe FSM Portable design Disadvantage: More effort (especially when design changes)

اسلاید 91: مرتضي صاحب الزماني 91FSM: Medvedev        Two Processes architecture RTL of MEDVEDEV is     ... begin      REG: process (CLK, RESET)     begin         -- State Registers Inference     end process REG ;      CMB: process (X, STATE)     begin        -- Next State Logic     end process CMB ;     Y <= S ; end RTL ;The output vector resembles the state vector:      Y = S          One Process architecture RTL of MEDVEDEV is     ... begin      REG: process (CLK, RESET)     begin         -- State Registers Inference with Logic Block     end process REG ;     Y <= S ; end RTL ;

اسلاید 92: مرتضي صاحب الزماني 92Medvedev Example (2-Process)architecture RTL of MEDVEDEV_TEST is     signal STATE,NEXTSTATE : STATE_TYPE ; begin      REG: process (CLK, RESET)     begin         if RESET=1 then             STATE <= START ;         elsif CLKevent and CLK=1 then             STATE <= NEXTSTATE ;         end if ;     end process REG;     CMB: process (A,B,STATE)  begin          case STATE is             when START  => if (A or B)=0 then                             NEXTSTATE <= MIDDLE ;                         end if ;             when MIDDLE => if (A and B)=1 then                             NEXTSTATE <= STOP ;                          end if ;             when STOP    => if (A xor B)=1 then                             NEXTSTATE <= START ;                          end if ;             when others => NEXTSTATE <= START ;         end case ;     end process CMB ;     -- concurrent signal assignments for output      (Y,Z) <= STATE ; end RTL ;

اسلاید 93: مرتضي صاحب الزماني 93Medvedev Example Waveform(Y,Z) = STATE => Medvedev machine

اسلاید 94: مرتضي صاحب الزماني 94FSM: Moore       Three Processes architecture RTL of MOORE is     ... begin      REG: -- Clocked Process      CMB: -- Combinational Process     OUTPUT: process (STATE)     begin         -- Output Logic     end process OUTPUT ; end RTL ;The output vector is a function of the state vector:     Y = f(S)       Two Processes architecture RTL of MOORE is     ... begin      REG: process (CLK, RESET)     begin         -- State Registers Inference with Next State Logic     end process REG ;     OUTPUT: process (STATE)     begin         -- Output Logic     end process OUTPUT ; end RTL ;

اسلاید 95: مرتضي صاحب الزماني 95Moore Examplearchitecture RTL of MOORE_TEST is     signal STATE,NEXTSTATE : STATE_TYPE ; begin     REG: process (CLK, RESET) begin         if RESET=1 then    STATE <= START ;         elsif CLKevent and CLK=1 then             STATE <= NEXTSTATE ;         end if ;     end process REG ;Since outputs depend only on the current state, no signals other than STATE appears in the sensitivity list.    CMB: process (A,B,STATE) begin                  case STATE is           when START => if (A or B)=0 then                             NEXTSTATE <= MIDDLE ;                          end if ;           when MIDDLE => if (A and B)=1 then                             NEXTSTATE <= STOP ;                          end if ;           when STOP    => if (A xor B)=1 then                             NEXTSTATE <= START ;                          end if ;           when others => NEXTSTATE <= START ;         end case ;     end process CMB ;     -- concurrent signal assignments for output     Y <= ‘1’ when STATE=MIDDLE else ‘0’ ;     Z <= ‘1’ when STATE=MIDDLE                  or STATE=STOP else ‘0’; end RTL ;

اسلاید 96: مرتضي صاحب الزماني 96Moore Example Waveform(Y,Z) changes simultaneously with STATE  Moore machine

اسلاید 97: مرتضي صاحب الزماني 97FSM: Mealy       Three Processes architecture RTL of MEALY is     ... begin     REG: -- Clocked Process     CMB: -- Combinational Process     OUTPUT: process (STATE, X)     begin         -- Output Logic     end process OUTPUT ; end RTL ;The output vector is a function of the state vector and the input vector:  Y = f(X,S)       Two Processes architecture RTL of MEALY is     ... begin     MED: process (CLK, RESET)     begin         -- State Registers Inference with Next State Logic     end process MED ;     OUTPUT: process (STATE, X)     begin         -- Output Logic     end process OUTPUT ; end RTL ;

اسلاید 98: مرتضي صاحب الزماني 98Mealy Examplearchitecture RTL of MEALY_TEST is     signal STATE,NEXTSTATE : STATE_TYPE ; begin  REG: · · ·   -- clocked STATE process  CMB: · · ·   -- Like Medvedev and Moore Examples  OUTPUT: process (STATE, A, B)   begin         case STATE is            when START   =>                                           Y <= 0 ;                                           Z <= A and B ;            when MIDLLE  =>                                           Y <= A nor B ;                                           Z <= 1 ;            when STOP     =>                                           Y <= A nand B ;                                           Z <= A or B ;            when others  =>                                           Y <= 0 ;                                           Z <= 0 ;         end case;     end process OUTPUT; end RTL ;

اسلاید 99: مرتضي صاحب الزماني 99Mealy Example (Another Code)architecture RTL of MEALY_TEST is     signal STATE,NEXTSTATE : STATE_TYPE ; begin  REG: · · ·   -- clocked STATE process  CMB: · · ·   -- Like Medvedev and Moore Examples -- Concurrent signal assignments for outputsY <= ‘1’ when (STATE = MIDDLE and (A or B) = ‘0’)or(STATE = STOP and (A and B) = ‘0’) else ‘0’; Z <= ‘1’ when (STATE = START and (A and B) = ‘1’)or (STATE = MIDDLE) or(STATE = STOP and (A or B) = ‘1’) else ‘0’; end RTL ;

اسلاید 100: مرتضي صاحب الزماني 100Mealy Example Waveform(Y,Z) changes with input => Mealy machine Note the spikes of Y and Z in the waveform

اسلاید 101: مرتضي صاحب الزماني 101Modeling AspectsMedvedev is too inflexible but less hardware (no combinational circuit for output)More effort to calculate state vector.Moore is preferred because of safe operationsince o/p depends only on state vector. next output values are stable long before the next clock edge.Mealy more flexible, but danger of Spikes Unnecessary long paths (maximum clock period) Combinational feed back loops

اسلاید 102: مرتضي صاحب الزماني 102Registered OutputAvoiding long paths and combinational loops. With one additional clock periodWithout additional clock period

اسلاید 103: مرتضي صاحب الزماني 103Registered Output Example (1)architecture RTL of REG_TEST is     signal Y_I , Z_I : std_ulogic ;     signal STATE,NEXTSTATE : STATE_TYPE ; begin    REG: · · ·   -- clocked STATE process     CMB: · · ·   -- Like other Examples     OUTPUT: process (STATE, A, B)     begin         case STATE is            when START   =>                                           Y_I<= 0 ;                                           Z_I<= A and B ;            · · ·     end process OUTPUT     -- clocked output process     OUTPUT_REG: process(CLK)    begin         if CLKevent and CLK=1 then          Y <= Y_I ;          Z <= Z_I ;         end if ;     end process OUTPUT_REG ; end RTL ;

اسلاید 104: مرتضي صاحب الزماني 104Reg. Output Example WaveformOne clock period delay between STATE and output changes. Input changes with clock edge result in an output change. (Danger of unmeant values )

اسلاید 105: مرتضي صاحب الزماني 105Registered Output Example (2)architecture RTL of REG_TEST2 is     signal Y_I , Z_I : std_ulogic ;     signal STATE,NEXTSTATE : STATE_TYPE ; begin REG: · · ·   -- clocked STATE process  CMB: · · ·   -- Like other Examples  OUTPUT: process ( NEXTSTATE , A, B)   begin         case NEXTSTATE is            when START   =>                                           Y_I<= 0 ;                                           Z_I<= A and B ;            · · ·   end process OUTPUT  OUTPUT_REG: process(CLK)   begin         if CLKevent and CLK=1 then          Y <= Y_I ;          Z <= Z_I ;         end if ;  end process OUTPUT_REG ; end RTL ;

اسلاید 106: مرتضي صاحب الزماني 106Reg. Output Example WaveformNo delay between STATE and output changes. Spikes of original Mealy machine are gone!

اسلاید 107: مرتضي صاحب الزماني 107Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLK دستگاههاي روي باس با اعلان bus idي mem_buffer (F3) دسترسي به باس را آغاز مي كنند.

اسلاید 108: مرتضي صاحب الزماني 108Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLK يك سيكل بعد, READ_WRITE = ‘1’ مي شود تا بگويد كه يك خواندن مي خواهد انجام شود (يا ‘0’ براي نوشتن).

اسلاید 109: مرتضي صاحب الزماني 109Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLKبراي خواندن ممكن است 4كلمه اي (burst read)باشد: بايد در مدت اولين سيكل, burst فعال باشد.

اسلاید 110: مرتضي صاحب الزماني 110Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLKكنترلر به 4 محل از بافر دسترسي مي يابد (به محلهاي بعدي بعد از فعال كردنهاي متوالي ready دسترسي مي يابد).

اسلاید 111: مرتضي صاحب الزماني 111Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLK كنترلر oe را براي mem_buffer در طول خواندن فعال مي كند و دو بايت پايين آدرس را در حالت burst افزايش مي دهد.

اسلاید 112: مرتضي صاحب الزماني 112Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLKنوشتن هميشه يك كلمه اي است.

اسلاید 113: مرتضي صاحب الزماني 113Case Study (Memory Controller)  FSMSRAMMemory ArrayAddressDataOEWEADDR1ADDR0BUS_IDResetREADYBURSTREAD_WRITECLKهنگام نوشتن we فعال مي شود و data در محلaddress نوشته مي شود. خواندن و نوشتن با اعلان ready خاتمه مي يابد.

اسلاید 114: مرتضي صاحب الزماني 114دياگرام حالتidleDecisionWriteread1read2read3read4readyRead_writeRead_writereadyready. burstreadyreadyready. burstreadysynch reset

اسلاید 115: مرتضي صاحب الزماني 115Memory Controller  براي همة حالتها مفروض است:stateready

اسلاید 116: مرتضي صاحب الزماني 116VHDL Code (2-process)library ieee;use ieee.std_logic_1164.all;entity memory_controller is port ( reset, read_write, ready, burst, clk : in std_logic; bus_id : in std_logic_vector(7 downto 0); oe, we : out std_logic; addr : out std_logic_vector(1 downto 0));end memory_controller;architecture state_machine of memory_controller istype StateType is (idle, decision, read1, read2, read3, read4, write);signal present_state, next_state : StateType;

اسلاید 117: مرتضي صاحب الزماني 117VHDL Codebeginstate_comb:process(reset, bus_id, present_state, burst, read_write, ready) begin if (reset = 1) then oe <= -; we <= -; addr <= --; next_state <= idle; else case present_state is when idle => oe <= 0; we <= 0; addr <= 00; if (bus_id = 11110011“ and ready = ‘1’) then next_state <= decision; else next_state <= idle; end if; when decision=> oe <= 0; we <= 0; addr <= 00; if (read_write = 1) then next_state <= read1; else --read_write=0 next_state <= write; end if; Don’t cares assigned to outputs  optimizedIn every case, a signal must be assigned to the outputs; otherwise, unwanted latches.

اسلاید 118: مرتضي صاحب الزماني 118 when read1 => oe <= 1; we <= 0; addr <= 00; if (ready = 0) then next_state <= read1; elsif (burst = 0) then next_state <= idle; else next_state <= read2; end if; when read2 => oe <= 1; we <= 0; addr <= 01; if (ready = 1) then next_state <= read3; else next_state <= read2; end if; when read3 => oe <= 1; we <= 0; addr <= 10; if (ready = 1) then next_state <= read4; else next_state <= read3; end if;

اسلاید 119: مرتضي صاحب الزماني 119VHDL Code when read4 => oe <= 1; we <= 0; addr <= 11; if (ready = 1) then next_state <= idle; else next_state <= read4; end if; when write => oe <= 0; we <= 1; addr <= 00; if (ready = 1) then next_state <= idle; else next_state <= write; end if; end case; end if;end process state_comb;

اسلاید 120: مرتضي صاحب الزماني 120VHDL Codestate_clocked:process(clk) begin if rising_edge(clk) then present_state <= next_state; end if;end process state_clocked;end;

اسلاید 121: مرتضي صاحب الزماني 121توليد خروجيها در ماشينهاي Moore  خروجيهايي كه از بيتهاي حالت به طور تركيبي ديكد شده اند: (كد قبل)Next-State LogicState RegistersOutput LogicInputsNext-StateCurrent-Stateoutputsمزايا:گويايي كدنگهداري آسانتراشكال:كند

اسلاید 122: مرتضي صاحب الزماني 122توليد خروجيها در ماشينهاي Moore  2) خروجيهايي كه از رجيسترهاي خروجي به طور موازي ديكد مي شوند:Next-State LogicState RegistersOutput LogicInputsNext-StateCurrent-Stateoutputsانتساب به خروجيها بايد در خارج ازپروسسي كه انتقال حالات در آن تعريف مي شود انجام گيرد.Output Registers

اسلاید 123: مرتضي صاحب الزماني 123  فرض: فقط براي addr اين كار را انجام مي دهيم (براي we و oe مشكل زماني نداريم)architecture state_machine of memory_controller is type StateType is (idle, decision, read1, read2, read3, read4, write); signal present_state, next_state : StateType; signal addr_d: std_logic_vector(1 downto 0); -- D-input to addr f-flopsbeginstate_comb:process(bus_id, present_state, burst, read_write, ready) begin case present_state is -- addr outputs not defined when idle => oe <= 0; we <= 0; -- addr is absent. if (bus_id = 11110011“ and ready = ‘1’) then next_state <= decision; else next_state <= idle; end if; when decision=> oe <= 0; we <= 0; if (read_write = 1) then next_state <= read1; else --read_write=0 next_state <= write; end if;

اسلاید 124: مرتضي صاحب الزماني 124  when read1 => oe <= 1; we <= 0; if (ready = 0) then next_state <= read1; elsif (burst = 0) then next_state <= idle; else next_state <= read2; end if; when read2 => oe <= 1; we <= 0; if (ready = 1) then next_state <= read3; else next_state <= read2; end if; when read3 => oe <= 1; we <= 0; if (ready = 1) then next_state <= read4; else next_state <= read3; end if;

اسلاید 125: مرتضي صاحب الزماني 125  when read4 => oe <= 1; we <= 0; if (ready = 1) then next_state <= idle; else next_state <= read4; end if; when write => oe <= 0; we <= 1; if (ready = 1) then next_state <= idle; else next_state <= write; end if; end case;end process state_comb; with next_state select -- D-input to addr flip-flops addr_d <= 01 when read2, -- defined here. 10 when read3, 11 when read4, 00 when others;

اسلاید 126: مرتضي صاحب الزماني 126  state_clocked:process(clk, reset) begin if reset = 1 then present_state <= idle; addr <= 00; -- asynchronous reset for addr flops elsif rising_edge(clk) then present_state <= next_state; addr <= addr_d; -- value of addr_d stored in addr end if;end process state_clocked;end state_machine;

اسلاید 127: مرتضي صاحب الزماني 127توليد خروجيها در ماشينهاي Mooreمشكلات:2 FF اضافه.براي انتشار بيتهاي حالت به FFهاي addr, از دو مدار تركيبي رد مي شود (اگر در PLD از 2 سلول استفاده كند مي تواند فركانس ماكزيمم را محدود كند)Next-State LogicState RegistersOutput LogicInputsNext-StateCurrent-StateoutputsOutput Registers

اسلاید 128: مرتضي صاحب الزماني 128توليد خروجيها در ماشينهاي Moore  3) خروجيهايي كه مستقيماً در بيتهاي حالت انكد شده اند (Medvedev) (مانند شمارنده ها):Next-State LogicState RegistersInputsNext-StateCurrent-StateoutputsState encoding بايد به دقت انجام شود.FFهاي بيشتري لازم دارد.براي خروجي به مدار ترکيبي نياز ندارد (سرعت بيشتر).

اسلاید 129: مرتضي صاحب الزماني 129State EncodingAddr(0)Addr(1)00Idle00decision00Read110Read201Read311Read400Writes2s1001001xxxxxx11000000فرض: فقط براي addr اين كار را انجام مي دهيم (براي we و oe مشكل زماني نداريم)

اسلاید 130: مرتضي صاحب الزماني 130State EncodingAddr(0)Addr(1)00Idle00decision00Read110Read201Read311Read400Writeاگر براي we و oe هم بخواهيم به همين صورت encode کنيم:weoe00000101010110s00100000

اسلاید 131: مرتضي صاحب الزماني 131VHDL Codearchitecture state_machine of memory_controller is-- state signal is a std_logic_vector rather than an enumeration type signal state : std_logic_vector(4 downto 0); constant idle : std_logic_vector(4 downto 0) := 00000; constant decision: std_logic_vector(4 downto 0) := 00001; constant read1 : std_logic_vector(4 downto 0) := 00100; constant read2 : std_logic_vector(4 downto 0) := 01100; constant read3 : std_logic_vector(4 downto 0) := 10100; constant read4 : std_logic_vector(4 downto 0) := 11100; constant write : std_logic_vector(4 downto 0) := 00010;beginstate_tr:process(reset, clk) begin -- One-process FSM if reset = 1 then state <= idle; elsif rising_edge(clk) then case state is -- outputs not defined here when idle => if (bus_id = 11110011) then state <= decision; end if; -- no else; implicit memory

اسلاید 132: مرتضي صاحب الزماني 132VHDL Code when decision=> if (read_write = 1) then state <= read1; else --read_write=0 state <= write; end if; when read1 => if (ready = 0) then state <= read1; elsif (burst = 0) then state <= idle; else state <= read2; end if; when read2 => if (ready = 1) then state <= read3; end if; -- no else; implicit memory

اسلاید 133: مرتضي صاحب الزماني 133 when read3 => if (ready = 1) then state <= read4; end if; -- no else; implicit memory when read4 => if (ready = 1) then state <= idle; end if; -- no else; implicit memory when write => if (ready = 1) then state <= idle; end if; -- no else; implicit memory when others => state <= -----; -- dont care if undefined state end case;end if;end process state_tr;-- outputs associated with register values we <= state(1); oe <= state(2); addr <= state(4 downto 3);end state_machine;

اسلاید 134: مرتضي صاحب الزماني 134 One-Hot EncodingNتا FF براي N حالت.مثال: يک FSM با 18 حالت.One-HotSequentialState00000000000000000100000State000000000000000001000001State100000000000000010000010State200000000000000100000011State300000000000001000000100State400000000000010000000101State500000000000100000000110State600000000001000000000111State700000000010000000001000State800000000100000000001001State900000001000000000001010State1000000010000000000001011State1100000100000000000001100State1200001000000000000001101State1300010000000000000001110State1400100000000000000001111State1501000000000000000010000State1610000000000000000010001State17

اسلاید 135: مرتضي صاحب الزماني 135 One-Hot EncodingState15State17State2cond3cond3cond1cond2فرض: بخشي از FSM:

اسلاید 136: مرتضي صاحب الزماني 136 One-Hot Encodingالف) Sequential Encodings4s3s2s1s0(بعدي)cond1cond2cond3….s4s3s2s1s0(جاري)state0state1011111 - - - - - - - - -00010state2...01111- - 0 - - - - - - - -01111state15state1601111- 1 - - - - - - - -10001state17State15State17State2cond3cond3cond1cond2

اسلاید 137: مرتضي صاحب الزماني 137 One-Hot Encodingالف) Sequential Encoding مدار ترکيبي بسيار بسيار پيچيده.

اسلاید 138: مرتضي صاحب الزماني 138 One-Hot Encodingمدار ترکيبي بسيار سادهاما تعداد FFها زياد18 معادلة بسيار ساده به جاي 5 معادلة بسيار پيچيده سطوح کمتر مدار بين رجيسترهاي حالت فرکانس بالاترمناسب براي FPGA.

اسلاید 139: مرتضي صاحب الزماني 139Power ReductionState assignment مناسب مي تواند توان مصرفي را کاهش دهد.مثلاً One-hot در هر سيکل، فقط 2 تغيير سيگنال لازم دارد.عوامل ديگر:تعداد زيادي رجيستر مي خواهد مدار منطقي توليد حالت بعدي بايد آزمايش کرد.Gray Encoding: براي FSMهاي شبيه شمارنده ها مناسب تر.

اسلاید 140: مرتضي صاحب الزماني 140Pipeliningايدة اصلي: عمليات datapath بزرگي را که در يک سيکل ساعت انجام مي شود به چند عمل کوچک که در چند سيکل انجام مي شوند تقسيم کنيم:Datapath OperationInputsoutputsRegistersRegisterstp= xPart 1InputsoutputsRegistersRegistersPart 1RegistersPart 1Registerstp= x/3tp= x/3tp= x/3

اسلاید 141: مرتضي صاحب الزماني 141Pipeliningf تقريباً 3 برابر مي شود (صرف نظر از زمانهاي tco و tsu براي رجيسترهاي (pipelinethroughput 3 برابر مي شود اما خروجيها 3 کلاک ديرتر حاضر مي شوند: latencyو نيز هزينة افزودن رجيسترها را دارد.بيشتر FPGAها مشکلي ندارند اما در CPLDها pipeline کمتر به کار مي رود.CPLDها در يک pass از logic array، عمليات زيادي را مي توانند انجام دهند

اسلاید 142: مرتضي صاحب الزماني 142Example: AMD AM2901src_op

اسلاید 143: مرتضي صاحب الزماني 143AMD AM2901library ieee;use ieee.std_logic_1164.all;use work.numeric_std.all;use work.am2901_comps.all;entity am2901 is port( clk, rst: in std_logic; a, b: in unsigned(3 downto 0); -- address inputs d: in unsigned(3 downto 0); -- direct data i: in std_logic_vector(8 downto 0); -- micro instruction c_n: in std_logic; -- carry in oe: in std_logic; -- output enable ram0, ram3: inout std_logic; -- shift lines to ram qs0, qs3: inout std_logic; -- shift lines to q y: buffer unsigned(3 downto 0); -- data outputs (3-state) g_bar,p_bar:buffer std_logic; -- carry generate, propagate ovr: buffer std_logic; -- overflow c_n4: buffer std_logic; -- carry out f_0: buffer std_logic; -- f = 0 f3: buffer std_logic); -- f(3) w/o 3-stateend am2901;

اسلاید 144: مرتضي صاحب الزماني 144architecture am2901 of am2901 is alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6); alias alu_ctl: std_logic_vector(2 downto 0) is i(5 downto 3); alias src_ctl: std_logic_vector(2 downto 0) is i(2 downto 0); signal ad, bd: unsigned(3 downto 0); signal q: unsigned(3 downto 0); signal r, s: unsigned(3 downto 0); signal alu_out: unsigned(3 downto 0);begin-- instantiate and connect componentsu1: ram_regs port map(clk => clk, rst => rst, a => a, b => b, alu_out => alu_out, dest_ctl => dest_ctl, ram0 => ram0, ram3 => ram3, ad => ad, bd => bd);u2: q_reg port map(clk => clk, rst => rst, alu_out => alu_out, dest_ctl => dest_ctl, qs0 => qs0, qs3 => qs3, q => q);u3: src_op port map(d => d, ad => ad, bd => bd, q => q, src_ctl => src_ctl, r => r, s => s);u4: alu port map(r => r, s => s, c_n => c_n, alu_ctl => alu_ctl, alu_out => alu_out, g_bar => g_bar, p_bar => p_bar, c_n4 => c_n4, ovr => ovr);u5: out_mux port map(ad => ad, alu_out => alu_out, dest_ctl => dest_ctl, oe => oe, y => y);-- define f_0 and f3 outputsf_0 <= 0 when alu_out = 0000 else Z;f3 <= alu_out(3);end am2901;

اسلاید 145: مرتضي صاحب الزماني 145Pipelined AM2901src_opبراي هماهنگي زماني خروجيها

اسلاید 146: مرتضي صاحب الزماني 146Pipelined AMD AM2901library ieee;use ieee.std_logic_1164.all;use work.numeric_std.all;use work.am2901_comps.all;entity am2901 is port( clk, rst: in std_logic; a, b: in unsigned(3 downto 0); -- address inputs d: in unsigned(3 downto 0); -- direct data i: in std_logic_vector(8 downto 0); -- micro instruction c_n: in std_logic; -- carry in oe: in std_logic; -- output enable ram0, ram3: inout std_logic; -- shift lines to ram qs0, qs3: inout std_logic; -- shift lines to q y: buffer unsigned(3 downto 0); -- data outputs (3-state) g_bar_q,p_bar_q:buffer std_logic; -- carry generate, propagate ovr_q: buffer std_logic; -- overflow c_n4_q: buffer std_logic; -- carry out f_0: buffer std_logic; -- alu_out = 0 f3: buffer std_logic); -- alu_out(3) w/o 3-stateend am2901;

اسلاید 147: مرتضي صاحب الزماني 147architecture am2901 of am2901 is alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6); alias alu_ctl: std_logic_vector(2 downto 0) is i(5 downto 3); alias src_ctl: std_logic_vector(2 downto 0) is i(2 downto 0); signal ad, bd: unsigned(3 downto 0); signal q: unsigned(3 downto 0); signal r, s: unsigned(3 downto 0); signal alu_out, alu_out_q: unsigned(3 downto 0);begin-- instantiate and connect componentsu1: ram_regs port map(clk => clk, rst => rst, a => a, b => b, alu_out => alu_out_q, dest_ctl => dest_ctl, ram0 => ram0, ram3 => ram3, ad => ad, bd => bd);u2: q_reg port map(clk => clk, rst => rst, alu_out => alu_out _q, dest_ctl => dest_ctl, qs0 => qs0, qs3 => qs3, q => q);u3: src_op port map(d => d, ad => ad, bd => bd, q => q, src_ctl => src_ctl, r => r, s => s);u4: alu port map(r => r, s => s, c_n => c_n, alu_ctl => alu_ctl, alu_out => alu_out, g_bar => g_bar, p_bar => p_bar, c_n4 => c_n4, ovr => ovr);u5: out_mux port map(ad => ad, alu_out => alu_out, dest_ctl => dest_ctl, oe => oe, y => y);-- define f_0 and f3 outputsf_0 <= 0 when alu_out _q = 0000 else Z;f3 <= alu_out _q(3);No change

اسلاید 148: مرتضي صاحب الزماني 148Pipelined AMD AM2901 process (clk) if (rising_edge(clk) then alu_out_q <= alu_out; g_bar_q <= g_bar; p_bar_q <= p_bar; ovr_q <= ovr; c_n4_q <= c_n4; end if; end process;end am2901;

اسلاید 149: مرتضي صاحب الزماني 149ReferencesWayne Wolf, FPGA-Based System Design, Prentice Hall, 2004.Ulrich Heinkel, Martin Padeffke, Werner Haas, Thomas Buerner, Herbert Braisz, Thomas Gentner, Alexander Grassmann, The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS , John Wiley & Sons, 2000.